With the development of information society, demand for flat display has been grown rapidly. Liquid crystal displays (LCDs) have advantages of small size, low energy consumption, and no radiation, and thus LCDs dominate the flat display market. However, the competition between LCD manufacturers is also huge. Thus, how to improve the display quality, reduce the defect product ratio, and reduce the manufacturing cost becomes the important guarantee to survive in the fierce competition. LCDs usually employ thin film transistors as the driver to achieve high speed, high brightness and high contrast ratio display effect.
Generally, the mainstream processes of manufacturing thin film transistors of bottom gate type may include four masks lithography process (4 Masks) or five masks lithography process (5 Masks). The “5 Masks” process includes a lithography process for forming gate electrodes (using a gate mask), a lithography process for forming the active layer (using an active mask), a lithography process for forming the source/drain electrodes (with a S/D mask), a lithography process for forming the via holes (using a via hole mask), and a lithography process for forming the pixel electrodes with a pixel mask). Each lithography process includes a thin film deposition process, an etching (including dry etching or wet etching) process, and a stripping process. Thus, to finish the “5 Masks” process, a process including the following sub-processes: thin film deposition process, photo-etching process, developing process, and stripping process, is looped 5 times.
The “4 Masks” process is developed by modifying the “5 Masks” process. The active mask and the S/D mask can be merged into a same mask by using gray tone photo-etching (using a gray tone mask), half tone photo-etching (using a half tone mask), or single slit mask process (using a single slit mask). That is, one mask could achieve the same etching result as the active mask and the S/D mask by adjusting the etching process.
FIG. 1 is a front schematic view of a thin film transistor array substrate manufactured using the known 4 masks process. FIG. 2 is a cross sectional schematic view taken along a line A-A in FIG. 1. Referring to FIGS. 1 and 2, a thin film transistor array substrate 20 includes a gate layout area 20a, a data electrode layout area 20b, and a pixel electrode layout area 20c. The thin film transistor array substrate 20 includes a glass substrate 21. On the glass substrate 21, a gate metal layer 22, a gate dielectric layer 23, an active layer 24 comprised of amorphous silicon (a-Si), a source metal layer 25a and a drain metal layer 25b formed on the active layer 24, a passivation layer 26, a via hole 27 formed above the drain metal layer 25b and in the passivation layer 26, and a transparent (indium tin oxide, ITO) pixel electrode layer 28 are sequentially formed. The transparent pixel electrode layer 28 is connected to the drain metal layer 25b via the via hole 27.
The data electrode layout area 20b includes the gate dielectric layer 23, the active layer 24 comprised of amorphous silicon (a-Si), the source metal layer 25a one the active layer 24, and the passivation layer 26 sequentially formed on the glass substrate 21. The pixel electrode layout area 20c includes the gate dielectric layer 23, the active layer 24 comprised of amorphous silicon (a-Si), the source metal layer 25a one the active layer 24, the passivation layer 26, via hole 27 formed in the passivation layer 26 and the transparent pixel electrode layer 28 sequentially formed on the glass substrate 21. The transparent pixel electrode layer 28 is connected to the drain metal layer 25b via the via hole 27.
As the amorphous silicon used to form the active layer 24 is a type of semiconductor material, the active layer 24 would produce photo current under the strong light irradiated from the backlight module of LCDs, and the photo current would change the pixel driving voltage provided by the transparent pixel electrode layer 28 for the liquid pixels. Finally, abnormal display of LCDs occurs, especially, severe image sticking phenomenon easily occurs during the performance testing process.